1. Field of the Invention
The present invention relates to a built-in self test circuit and a test method for a storage device embedded in a semiconductor integrated circuit.
2. Description of the Related Art
A method of building a built-in self test (Referred to as “BIST” hereinafter) circuit into a semiconductor integrated circuit and using the BIST to detect manufacturing defects of memory devices, in shipping tests of semiconductor integrated circuits, is generally performed. As a method of detecting defects using the BIST, BIST circuits with compactors, which compact output data of the memory devices, subsequently provide compacted results to an LSI tester, and determine whether or not the semiconductor integrated circuit is defective, exist. As another method of detecting defects using the BIST, BIST circuits with comparators, which compare output data with the expected value generated in the BIST circuit, also exist.
Further, a fault diagnosis, which analyzes fault locations in a memory device, is also performed using the BIST circuit. In a case in which defects have been detected in the BIST, operation of the BIST is stopped in order to perform the fault diagnosis, and output data at the address at which a defect has been detected is output to an external LSI tester as diagnostic data.
Generally, on BIST, first “0” or “1” is written into all memory cells of the memory devices on which testing is performed, and afterward, memory output is observed and analyzed for defect detection. For example, in a system which uses a test algorithm termed 13N march, in a case in which, first, “0” has been written into all memory cells, “0” reading operation, “1” write operation, and “1” reading operation is performed for each address. On comparator-type BIST, data that has been read is stored in a register, and the BIST and fault diagnosis is performed by comparing the data stored in the register with the expected value. At this time, data that has been read by the “0” read operation at address m is stored in the register at a clock cycle identical to that of the “1” write operation at the address m (m: an integer from 0 and above). And the data that has been read by the “1” read operation at the address m is stored in the register at a clock cycle identical to that of the “0” read operation at the next address; m+1 for ascending address increment, and m−1 for descending.
In a case in which the data read from the memory device by the “1” read operation fails to match the expected value at an address m in diagnosis mode, it is necessary to stop the operation of the BIST in order to observe the fail data, which is needed for the fault diagnosis, to the LSI tester. And after the fail data has been output to the LSI tester, operation of the BIST is resumed. Because of this, the data read from the memory device by the “0” read operation at the address m+1 is not stored in the register during the operation of the BIST is stopped, but is stored in the register after the operation of the BIST has been resumed. Put plainly, the interval from memory data output on the “0” read operation at the address m+1, to the capturing of the data in the register is long compared to a case in which the operation of the BIST is not stopped. Therefore, it may not be possible to detect delay faults, in a case in which there is a delay fault of the memory data output on the “0” read operation at the address m+1. Because of this, there existed a problem of incompleteness of a fail bit map produced from the fault diagnosis results.
Also, with the above stated method, fault is detected after memory output data has once been stored in the register. Because of this, it takes more than 1 clock cycle from memory read operation to fault detection. And the register contents will be overwritten by incoming data read from the memory device before holding the BIST operation. Therefore, in order to observe fail data to the LSI tester it is necessary to prepare a separate register for data preservation. In short, area size of the test circuit increases because of the necessary save-only register.